Various imager circuits have been proposed such as charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have light-sensing elements, typically referred to as “pixels” and readout circuitry that outputs signals indicative of the light sensed by the pixels.
A CMOS imager, for example, includes a focal plane array of pixel cells; each cell includes a photodetector (e.g., a photogate, photoconductor or a photodiode) overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photodetector is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photodetector to the floating diffusion region and another transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference.
FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above, or as other known pixel cell circuits. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines is provided for the entire array 200. The row lines are selectively activated in sequence by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated in sequence for each row activation by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel.
The CMOS imager 908 is operated by a control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. Control circuit 250 also controls the row and column driver circuitry 210, 260 so that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the floating diffusion region when it is reset by the reset transistor and a pixel image signal Vsig, which is taken off the floating diffusion region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, to produce a differential signal Vrst−Vsig for each pixel. Vrst−Vsig represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 275. The digitized pixel signals are fed to an image processor 280 to form a digital image output. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst−Vsig can be amplified as a differential signal and directly digitized by a differential analog-to-digital converter.
FIG. 2 illustrates a known four transistor (4T) CMOS imager pixel cell 100. Pixel cell 100 includes a photodiode 102 connected to a transfer transistor 104. The transfer transistor 104 is also connected to floating diffusion region 108. Both a reset transistor 106 and a source follower transistor 110 are connected to floating diffusion region 108. A row select transistor 112 is connected to source follower transistor 110. The active elements of pixel cell 100 perform the functions of (1) photon to charge conversion by photodiode 102; (2) resetting the floating diffusion region to a known state before the transfer of charge to it by reset transistor 106; (3) transfer of charge to the floating diffusion region 108 by the transfer transistor 104; (4) selection of the cell 100 for readout by row select transistor 112; and (5) output and amplification of a signal representing a reset voltage (i.e., Vrst) and a pixel signal voltage (i.e., Vsig) based on the photo converted charges by source follower transistor 110. The pixel cell 100 of FIG. 2 is formed on a semiconductor substrate as part of an imager device pixel array (e.g., array 200 of FIG. 1).
FIG. 3 illustrates a typical pixel readout circuit 300. Readout circuit 300 includes the source follower transistor 110 of pixel 100, row select transistor 112 of pixel 100, current source device 320, bias generator 310, and column sample and hold network 330, which includes sampling switches SHR and SHS and column sampling capacitors Cshr and Cshs. Current source device 320 provides a constant current for pixel source follower transistor 110. Devices 320 and 110 jointly form a common-drain source follow gain stage, which transfers signal from pixel array 100 FD node to column sample and hold network 330.
Typically, the current source device 320 is implemented by connecting two transistors 115 and 117 in series, as shown in FIG. 3. In this configuration, transistor 115 is driven by a digital buffer, and therefore transistor 115 is operated as a switch that is either on or off. When transistor 115 is turned on, transistor 115 is operated in the ohmic region, and transistor 117 is operated in the saturation region. This configuration is called “simple current source”.
For advanced image sensors, the design of the current source device 320 is critical because the transfer gain of the pixel source follower transistor 110 is sensitive to the current level of source device 320. Small variations on the current level would alter the source-follower transfer gain and cause undesired nonlinearity and column-wise fixed pattern noise.
Typically, the “simple current source” configuration as shown in FIG. 3 has a relatively small output resistance resulting in a relatively large current variation due to signal swing at source follower output node. This signal dependency may modify the source follower transfer gain and cause nonlinearity and column-wise fixed pattern noise.
A possible way of increasing the output resistance of the simple current source is to operate transistor 115 in the saturation region, such that transistors 115 and 117 form a well known “cascode current source” configuration. The output resistance of the cascode current source is increased by the small signal voltage gain (gm/gds) of transistor 115, which reduces non-linearity and column-wise fixed pattern noise. However, in order to keep both transistors 115 and 117 in the saturation region, the minimum terminal voltage (Vo, min) of the cascode current source has to be increased. As a result, the allowed signal swing of pixel source follower device 110 may need to be reduced.
It is apparent that the two current source configurations each have advantages and disadvantages. A simple current source is suitable for pixels with a high output signal swing or low power supply application, while the cascode current source is superior in reducing nonlinearity and column-wise fixed pattern noise. Thus, the selection of the current source configuration may not be easily determined at design time. With advanced imager development and manufacturing flow, in order to achieve an optimal design, several candidates of photodiode and pixel are often tested on the same readout circuitry, and therefore the source follower signal swing may be undetermined at the design phase. In addition, the power supply range of the imager may be slightly changed from applications to applications, and hence the selection of the optimal current source configuration may need to be modified according to the applications.
Accordingly, there is a need and desire for an imager with flexibility in selecting the current source configuration. Such flexibility improves imager readout performance by optimizing pixel selection, readout linearity, and column-wise fixed pattern noise according to specific application needs.